• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention discloses a static random access memory cell having a reduced cell size and method of manufacturing the same. According to the invention, the SRAM cell includes: a word line and a bit line; an access device connected to the word and bit lines, wherein in case that the word line is selected, the access device outputs data inputted from the bit line; a pull-up device connected to the access device as well as to a predetermined power voltage, wherein the pull-up device operates in pull-up manner according to the data inputted from the access device; and a pull-down device connected to the access device and the pull-up device as well as to a ground, wherein the pull-down device operates in pull-down manner according to the data inputted from the access devices.
    公开号:US20010001322A1
    申请号:US09/756,060
    申请日:2001-01-08
    公开日:2001-05-17
    发明作者:Jae-Kap Kim
    申请人:Jae-Kap Kim；
    IPC主号:H01L27-11
    专利说明:
    [1] 1. 1. Field of the Invention
    [2] 2. The present invention relates to a semiconductor memory device and method of manufacturing the same, and more particularly, to a static random access memory cell having a reduced cell size and method of manufacturing the same.
    [3] 3. 2. Discussion of Related Art
    [4] 4. A SRAM is a significant memory device due to its high speed, low power consumption, and simple operation. The The memory cell of the SRAM is constituted of flip-flop circuit. In addition, unlike a DRAM, the SRAM does not need to regularly refresh the stored data and has a straight forward design. The SRAM cell includes: two pull-up devices; two access devices; and two pull-down devices. The SRAM cell further classified as a full CMOS cell, a high road resistor (HRL), or thin film transistor(TFT) cell according to the load types of the pull-up device.
    [5] 5. The TFT cell utilizes P-channel TFT as the pull-up device and it is being developed in 4 Mb or 16 Mb SRAM cell. The SRAM cell with TFT cell structure has low power consumption and a good stability during a stand-by operation in contrast to the SRAM cell with HRL cell structure. In addition, it has outstanding degree of high integration in contrast to the SRAM cell with the full CMOS cell structure having a bulk structure. As the SRAM cell with TFT cell structure, however, has a complex manufacturing process, the SRAM cell with full CMOS cell structure is manufactured to a higher degree. In contrast to the SRAM cell with TFT cell structure, the SRAM cell with the full CMOS cell structure has the simple manufacturing process. In addition, the SRAM cell with the full CMOS cell structure has high current during its operation and good stability.
    [6] 6.FIG. 1 is a conventional circuit diagram of a SRAM cell with full CMOS cell structure. In FIG. 1, WL denotes a word line, and BL1 and BL2 denote bit lines. N1 and N2 denote nodes, and VDD is a power voltage. VSS is a ground voltage. UT1 and UT2 are pull-up transistors that comprise a P-channel MOS (PMOS) transistor. DT1 and DT2 are pull-down transistors that comprise N channel MOS (NMOS) transistor. AT1 and AT2 are access transistors that comprise the NMOS transistor.
    [7] 7. A first CMOS inverter includes the PMOS transistor for use in the pull-up transistor UT1, and the NMOS transistor for use in pull-down transistor DT1. A second CMOS inverter includes the PMOS transistor for use in the pull-up transistor UT2 and the NMOS transistor for use in the pull-down transistor DT2. An output of the first CMOS inverter is connected with an input of the second CMOS inverter at the node N1. An input of the first CMOS inverter is connected with an output of the second CMOS inverter at the node N2. The sources of the NMOS transistors for use in the access transistors AT1 and AT2, are respectively connected to the bit lines BL1 and BL2, drains of the above NMOS transistors respectively connected to the nodes N1 and N2, and gates the above NMOS transistors respectively connected to the word line WL.
    [8] 8. In the above-described SRAM cell with full CMOS cell structure, however, its unit cell is constituted of four NMOS transistors and two PMOS transistors, so that its cell size is large. Accordingly, as the SRAM cell with full CMOS cell structure has difficulty in reducing the cell size below a predetermined level, and it is difficult to manufacture a highly integrated memory device. SUMMARY OF THE INVENTION
    [9] 9. Accordingly, an object of the present invention is to provide an SRAM cell which can reduce the number of transistors constituting a memory cell thereby realizing higher integration of memory device, and a method of manufacturing the same.
    [10] 10. To achieve the above objects, a SRAM cell according to the present invention includes: a word line and a bit line; an access device connected to the word and bit lines, wherein in case that the word line is selected, the access device outputs data inputted from the bit line; a pull-up device connected to the access device as well as to a predetermined power voltage, wherein the pull-up device operates in pull-up manner according to data inputted from the access device; and a pull-down device connected to the access device and the pull-up device as well as to a ground, wherein the pull-down device operates in pull-down manner according to data inputted from the access devices.
    [11] 11. In this embodiment, the access device is an NMOS transistor, the pull-up device is an NMOS transistor, and the pull-down device is a PMOS transistor.
    [12] 12. Furthermore, according to the present invention, there is provided a SRAM cell comprising: a semiconductor substrate, wherein a first and a second conductivity type wells are formed therein, a first active region is defined in the well of the first conductivity type and a second active region is defined in the well of the second conductivity type, by the field oxide layer; a gate insulating layer formed on the first and second active regions; first and second gates formed on the first active region and a third gate formed on the second active region; impurity diffusion regions of the second conductivity type formed in the first active region of both sides of each of the first and second gates, wherein the one of the impurity diffusion regions is a common region; impurity diffusion regions of the first conductivity type formed in the second active region of both sides of the third gate; an intermediate insulating layer formed on the overall substrate and having contact holes which expose predetermined portions of the impurity diffusion regions of the first and second conductivity types, predetermined portions of the second gate adjacent to the common impurity diffusion region of the second conductivity type, and predetermined portions of one side of the third gate; and metal interconnection layers each being in contact to the impurity diffusion regions of the first and second conductivity types and the second and third gates, through the contact holes.
    [13] 13. Furthermore, the SRAM cell according to the present invention is fabricated by following process. A semiconductor substrate is provided. A first and a second conductivity type wells are formed in the substrate; Isolating layers are formed to define a first active region in the first conductivity well and a second active region in the second conductivity well. A gate insulating layer is formed on the first and second active regions. First and second gates are formed on the first active region which has the gate insulating layer formed thereon, and a third gate on the second active region which has the gate insulating layer formed thereon. Impurity diffusion regions of the second conductivity type are formed in the first active region of both sides of each of the first and second gates so that the one of the impurity diffusion regions is common between the first and second gates. Impurity diffusion regions of the first conductivity type are formed in the second active region of both sides of the third gate. An intermediate insulating layer is formed on the overall substrate. The intermediate insulating layer is etched to expose predetermined portions of each of the impurity diffusion regions of the first and second conductivity types, a predetermined portion of the second gate adjacent to the common impurity diffusion region of the second conductivity type, and a predetermined portion of the third gate to one side, thereby forming contact holes. A metal layer is deposited to filling the contact holes on the intermediate layer. Metal interconnection layers are formed to contact the impurity diffusion regions of the first and second conductivity types and the second and third gates by patterning the metal layer.
    [14] 14. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE ATTACHED DRAWINGS
    [15] 15. The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
    [16] 16. In the drawings:
    [17] 17.FIG. 1 is an equivalent circuit diagram of a conventional SRAM cell with full CMOS cell structure;
    [18] 18.FIG. 2 is an equivalent circuit diagram of the SRAM cell with the full CMOS cell structure according to an embodiment of the present invention;
    [19] 19.FIG. 3 is a layout of the SRAM cell with the full CMOS cell structure according to an embodiment of the present invention; and
    [20] 20.FIGS. 4A to 4C are cross sectional views showing a method of manufacturing the SRAM cell according to an embodiment of the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENT
    [21] 21. A preferred embodiment according to the present invention is described below with reference the attached drawings.
    [22] 22. As illustrated in FIG. 2, the SRAM cell according to the present invention is constituted of three transistors.
    [23] 23. In FIG. 2, WL is a word line, BL is a bit line, and UT is a pull-up transistor made of a NMOS transistor. Vf is a predetermined power voltage, and VSS is a ground voltage. DT is a pull-down transistor made of PMOS transistor. AT is the access transistor made of the NMOS transistor, and N is a node.
    [24] 24. The sources of the NMOS transistor for use in pull-up transistor UT, of the PMOS transistor for use in the pull-down transistor DT, and of the NMOS transistor for use in the access transistor AT are connected to one another at the node N. The gates of the pull-up transistor UT and the pull-down transistor DT are connected to the node N. A predetermined power voltage Vf is applied to the drain of the pull-up transistor UT. Drain of the pull-down transistor DT is grounded to VSS. The Gate of the access transistor AT is connected to the word line WL, and the drain thereof is connected to the bit line BL.
    [25] 25. In the above described SRAM cell, an operation to store data in a HIGH state at node N is as follows. In case that the word line WL is turned on and voltage in HIGH level is input to the bit line BL, the pull-down transistor DT is turned off and the pull-up transistor UT is turned on. Therefore, data at a HIGH state is stored at node N. Here, the voltage of the predetermined power voltage Vf is higher, as a threshold voltage of the pull-up transistor UT, than that which is applied to the bit line BL a threshold voltage of the pull-up transistor UT. In case that the word line WL is turned on and data in a LOW state is input to the bit line BL to store data in a LOW state, the pull-up transistor UT is turned off and the pull-down transistor DT is turned on. Therefore, data in a LOW state is stored at the node N.
    [26] 26. In FIG. 3, reference numeral 10 denotes a P well and reference numeral 20 denotes N well. A1, A2 and B are active regions, 30 a and 30 b are gate line. 40 a to 40 d are N+impurity diffusion regions and 50 a and 50 b are P+ impurity diffusion regions. C1 to C6 are contact regions.
    [27] 27. As illustrated in FIG. 3, in the SRAM cell, a P well 10 and a N well 20 are joined and horizontally extended each other on the substrate 1. The active region A1 is horizontally disposed at the P well 10. The active region A2 and B are disposed at the N well 20 at a predetermined interval each other to be parallel to the active region A1. The gate (word line) 30 b is disposed in a perpendicular direction to partly cover the active region A1. The gate (word line) 30 a is vertically arranged to thereby cross the active region A1 and pass through the N well 20 between the active-region A2 and B. N+impurity diffusion regions 40 a to 40 d are formed in the active region A1 on both sides of each gate (word line) 30 a and 30 b and the active region A2. 40 a and 40 c become drain regions and 40 b becomes common source region of the access transistor AT and the pull-up transistor UT, so that NMOS transistors for use in the access transistor AT and the pull-up transistor UT are achieved. 40 d is a N well junction region. P+impurity diffusion regions 50 a and 50 b are formed in the active region A2 on both sides of the gate 30 b. 50 a becomes a drain region, 50 b becomes a source region thereby achieving the pull-down PMOS transistor DT. C1 to C6 are contact regions. C1 is the contact region of the drain region 40 a of the access transistor AT, and the bit line (refer to FIG. 2) C2 is the contact region of the common source 40 b of the access transistor AT and the pull-up transistor UT, and the gate 30 b. C3 is the contact region of the drain 40 c of the pull-up transistor UT and the predetermined power voltage (refer to FIG. 2). C4 is the contact region of the drain 50 a of the pull-down transistor DT and the ground voltage (refer to FIG. 2). C5 is the contact region of the source 50 b of the pull-down transistor DT and the gate 30 b. C6 is the contact region of the N well junction region 40 d and the power voltage (not shown). The common source region 40 b of the access transistor AT and pull-up transistor UT is connected to the source region 50 b of the pull-down transistor DT by the contact regions C2 and C4.
    [28] 28. With reference to FIGS. 4A to 4C, a method for manufacturing the SRAM cell will be described below. FIGS. 4A to 4C are cross sectional views of FIG. 3 taken along lines X-X′. Reference numeral 2 denotes a field oxide layer, 3 is a gate insulating layer, and 4 is an intermediate insulating layer.
    [29] 29. As illustrated in FIG. 4A, P well 10 and N well 20 are formed in the semiconductor substrate 1. The field oxide layers 2 a and 2 b are formed on the substrate 1 by the well-known LOCOS (LOCal Oxidation of Silicon) method. Therefore, the active region A1 of the access transistor AT is defined in the P well 10, and the active regions B and A2 are defined in the N well 20.
    [30] 30. As illustrated in FIG. 4B, the gate insulating layer and the polysilicon layer are sequentially deposited and patterned on the structure of FIG. 4A. Therefore, the gate insulating layer 3 and the gates 30 a 1, 30 b 1 and 30 b 2 are formed on the active regions A1 and A2, and the gate 30 a 2 is formed on the field oxide layer 2 b. A N+impurity ion is implanted into the active regions A1 and A2 of both sides of the gates 30 a 1 and 30 a 2, so that the N+impurity diffusion regions 40 a to 40 d are formed. 40 a and 40 c become each drain regions, and 40 d becomes the common source region, thereby forming the NMOS transistors of which source is common. 40 d becomes the N well junction region. Thereafter, P+impurity ions are implanted into the active region B of both sides of the gate 30 b, so that the P+impurity diffusion regions 50 a and 50 b are formed. 50 a becomes a drain and 50 b becomes a source, so that the PMOS transistor for use in the pull-down transistor DT is achieved.
    [31] 31. As illustrated in FIG. 4C, the intermediate insulating layer 4 is deposited on the structure of FIG. 4B. The intermediate insulating layer 4 is etched to expose the predetermined portions of the source regions 40 a, 40 b and 40 c and drain region 50 a and 50 b and the N well junction region 40 d, and to also expose the gates 30 b 1 and 30 b 2 of the pull-up transistor UT and the pull-down transistor DT, thereby forming the contact holes (not shown). Here, the etching of the intermediate layer 4 is carried out so that the gate 30 b 1 and source 40 b of the pull-up transistor UT are exposed though a shared contact hole, and the gate 30 b 2 and source 50 b of the pull-down transistor DT are also exposed through a shared contact hole.
    [32] 32. A metal layer is deposited to fill the contact holes on the intermediate insulating layer 4 and then patterned, so that the metal interconnection layers 60 a to 60 f are formed. Accordingly, the gate 30 b 1 of the pull-up transistor UT and the source region 40 b thereof are connected with each other, and the gate 30 b 2 of the pull-down transistor DT and the source region thereof are connected with each other.
    [33] 33. According to the present invention, the SRAM cell with the full CMOS cell is realized with two NMOS transistors and one PMOS transistor, so that the cell size is reduced outstandingly. Accordingly, it is possible to realize the highly integrated SRAM cell.
    [34] 34. It will be apparent to those skilled in the art that various modifications and variations can be made in the SRAM cell and manufacturing method thereof of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
    权利要求:
    Claims (17)
    [1" id="US-20010001322-A1-CLM-00001] 1. A SRAM cell comprising:
    a word line and a bit line;
    an access device connected to the word and bit lines, wherein in case that the word line is selected, the access device outputs data inputted from the bit line;
    a pull-up device connected to the access device as well as to a predetermined power voltage, wherein the pull-up device operates in pull-up manner according to data inputted from the access device; and
    a pull-down device connected to the access device and the pull-up device as well as to a ground, wherein the pull-down device operates in pull-down manner according to data inputted from the access devices.
    [2" id="US-20010001322-A1-CLM-00002] 2. The SRAM cell according to
    claim 1 , wherein the access device is an NMOS transistor.
    [3" id="US-20010001322-A1-CLM-00003] 3. The SRAM cell according to
    claim 2 , wherein the gate of the NMOS transistor is connected to the word line, drain thereof is connected to the bit line, and the source thereof is connected to the pull-up and pull-down devices.
    [4" id="US-20010001322-A1-CLM-00004] 4. The SRAM cell according to
    claim 1 , wherein the pull-up device is an NMOS transistor.
    [5" id="US-20010001322-A1-CLM-00005] 5. The SRAM cell according to
    claim 4 , wherein the gate of the NMOS transistor is connected to the access device, a predetermined power voltage is applied to the drain thereof; and the source thereof is connected to the pull-down device.
    [6" id="US-20010001322-A1-CLM-00006] 6. The SRAM cell according to
    claim 5 , wherein the predetermined power voltage is higher, as the threshold voltage of the NMOS transistor, than the voltage signal of the bit line.
    [7" id="US-20010001322-A1-CLM-00007] 7. The SRAM cell according to
    claim 1 , wherein the pull-down device is a PMOS transistor.
    [8" id="US-20010001322-A1-CLM-00008] 8. The SRAM cell according to
    claim 7 , wherein the gate of the PMOS transistor is connected to the access device, the source thereof is connected to the pull-up device, and the drain thereof is grounded.
    [9" id="US-20010001322-A1-CLM-00009] 9. The SRAM cell according to
    claim 1 , wherein the access device comprises of a first NMOS transistor, the pull-up device comprising of a second NMOS transistor, and the pull-down device comprising of a PMOS transistor.
    [10" id="US-20010001322-A1-CLM-00010] 10. The SRAM cell according to
    claim 9 , wherein: sources of the first and second NMOS transistors and the PMOS transistor are connected to one node; the gate of the first NMOS transistor is connected to the word line and the drain thereof is connected to the bit line; the gate of the second NMOS transistor is connected with the gate of the PMOS transistor and the gates thereof are connected to the node; the predetermined power voltage is applied to the drain of the second NMOS transistor; and the drain of the PMOS transistor is grounded.
    [11" id="US-20010001322-A1-CLM-00011] 11. The SRAM cell according to
    claim 10 , wherein the predetermined power voltage is higher as the threshold voltage of the second NMOS transistor than the voltage signal of the bit line.
    [12" id="US-20010001322-A1-CLM-00012] 12. A SRAM cell, comprising:
    a semiconductor substrate, wherein a first and a second conductivity type wells are formed therein, a first active region is defined in the well of the first conductivity type and a second active region is defined in the well of the second conductivity type, by the field oxide layer;
    a gate insulating layer- formed on the first and second active regions;
    first and second gates formed on the first active region and a third gate formed on the second active region;
    impurity diffusion regions of the second conductivity type formed in the first active region of both sides of each of the first and second gates, wherein the one of the impurity diffusion regions is a common region;
    impurity diffusion regions of the first conductivity type formed in the second active region of both sides of the third gate.
    [13" id="US-20010001322-A1-CLM-00013] 13. The SRAM cell according to
    claim 12 , further comprising:
    an intermediate insulating layer formed on the overall substrate and having contact holes which expose predetermined portions of the impurity diffusion regions of the first and second conductivity types, predetermined portions of the second gate adjacent to the common impurity diffusion region of the second conductivity type, and predetermined portions of one side of the third gate; and
    metal interconnection layers each being in contact to the impurity diffusion regions of the first and second conductivity types and the second and third gates, through the contact holes.
    [14" id="US-20010001322-A1-CLM-00014] 14. The SRAM cell according to
    claim 13 , wherein the second gate is connected with the common impurity diffusion region of the second conductivity type by the metal interconnection layer.
    [15" id="US-20010001322-A1-CLM-00015] 15. The SRAM cell according to
    claim 13 , wherein the third gate is connected with the impurity diffusion region of the first conductivity type of the one side by the metal interconnection layer.
    [16" id="US-20010001322-A1-CLM-00016] 16. A method of manufacturing SRAM cell, comprising the steps of:
    providing a semiconductor substrate;
    forming a first and a second conductivity type wells in the substrate;
    forming isolating layers to define a first active region in the first conductivity well and a second active region in the second conductivity well;
    forming a gate insulating layer on the first and second active regions;
    forming first and second gates on the first active region which has the gate insulating layer formed thereon, and a third gate on the second active region which has the gate insulating layer formed thereon;
    forming impurity diffusion regions of the second conductivity type in the first active region of both sides of each of the first and second gates so- that the one of the impurity diffusion regions is common between the first and second gates; and
    forming impurity diffusion regions of the first conductivity type in the second active region of both sides of the third gate.
    [17" id="US-20010001322-A1-CLM-00017] 17. The SRAM cell according to
    claim 11 , further comprising the steps of:
    forming an intermediate insulating layer on the overall substrate;
    etching the intermediate insulating layer to expose predetermined portions of each of the impurity diffusion regions of the first and second conductivity types, a predetermined portion of the second gate adjacent to the common impurity diffusion region of the second conductivity type, and a predetermined portion of the third gate to one side, thereby forming contact holes; and
    depositing a metal layer to filling the contact holes on the intermediate layer;
    forming metal interconnection layers to contact the impurity diffusion regions of the first and second conductivity types and the second and third gates by patterning the metal layer.
    类似技术:
    公开号 | 公开日 | 专利标题
    US6372565B2|2002-04-16|Method of manufacturing SRAM cell
    USRE46272E1|2017-01-10|Semiconductor memory
    US7671422B2|2010-03-02|Pseudo 6T SRAM cell
    US5266507A|1993-11-30|Method of fabricating an offset dual gate thin film field effect transistor
    US6801449B2|2004-10-05|Semiconductor memory device
    US6359804B2|2002-03-19|Static semiconductor memory cell formed in an n-well and p-well
    US6606276B2|2003-08-12|SRAM device using MIS transistors
    US5521860A|1996-05-28|CMOS static memory
    JP2958909B2|1999-10-06|SRAM cell and method of manufacturing the same
    US6147385A|2000-11-14|CMOS static random access memory devices
    US6479905B1|2002-11-12|Full CMOS SRAM cell
    EP0506089B1|1997-11-19|Static random access type semiconductor memory device
    JP2998679B2|2000-01-11|Semiconductor memory device and method of manufacturing the same
    US6025253A|2000-02-15|Differential poly-edge oxidation for stable SRAM cells
    US5960278A|1999-09-28|Method of manufacturing SRAM cell
    US5966321A|1999-10-12|SRAM cell having increased cell ratio
    KR100325464B1|2002-02-25|Method of fabricating cmos memory device with self aligned metal plug
    KR100214842B1|1999-08-02|Semiconductor device and its fabrication process
    KR100362192B1|2002-11-23|A full CMOS SRAM cell having butting contact structure
    KR100511905B1|2005-09-02|Semiconductor device and method for manufacturing the same
    KR20010058346A|2001-07-05|Sram cell and method for fabricating the same
    同族专利:
    公开号 | 公开日
    US6204538B1|2001-03-20|
    JPH1070201A|1998-03-10|
    JP3020199B2|2000-03-15|
    TW359876B|1999-06-01|
    KR980006407A|1998-03-30|
    US6372565B2|2002-04-16|
    KR100230740B1|1999-11-15|
    US5907502A|1999-05-25|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20050166628A1|2002-08-16|2005-08-04|Newman Michael D.|Method for surface crust freezing of food product|
    US20070136640A1|2005-12-14|2007-06-14|Jarrar Anis M|Defect detection and repair in an embedded random access memory|
    US20080157221A1|2006-12-27|2008-07-03|Yong-Geun Lee|Structure of semiconductor device for decreasing chip area and manufacturing method thereof|
    US8878307B2|2005-02-24|2014-11-04|Sony Corporation|Shared contacts for MOSFET devices|JPS58130560A|1982-01-29|1983-08-04|Hitachi Ltd|Semiconductor memory integrated circuit|
    JPH03234059A|1990-02-09|1991-10-18|Sony Corp|Semiconductor memory|
    KR100199258B1|1990-02-09|1999-06-15|가나이 쓰도무|Semiconductor integrated circuit device|
    US5376816A|1992-06-24|1994-12-27|Nec Corporation|Bi-cmos integrated circuit device having buried region use in common for bipolar and mos transistors|
    US5330929A|1992-10-05|1994-07-19|Motorola, Inc.|Method of making a six transistor static random access memory cell|
    US5373170A|1993-03-15|1994-12-13|Motorola Inc.|Semiconductor memory device having a compact symmetrical layout|
    JP2682393B2|1993-08-13|1997-11-26|日本電気株式会社|Static type semiconductor memory device|
    US5394358A|1994-03-28|1995-02-28|Vlsi Technology, Inc.|SRAM memory cell with tri-level local interconnect|
    JP3588622B2|1994-07-20|2004-11-17|富士通株式会社|Semiconductor device and manufacturing method thereof|
    US5426324A|1994-08-11|1995-06-20|International Business Machines Corporation|High capacitance multi-level storage node for high density TFT load SRAMs with low soft error rates|
    KR100230740B1|1996-06-29|1999-11-15|김영환|A sram and manufacturing method thereof|KR100230740B1|1996-06-29|1999-11-15|김영환|A sram and manufacturing method thereof|
    US6487107B1|1999-09-29|2002-11-26|Infineon Technologies Ag|Retention time of memory cells by reducing leakage current|
    KR100301059B1|1999-07-20|2001-11-01|윤종용|Full CMOS SRAM cell|
    JP2001068564A|1999-08-30|2001-03-16|Mitsubishi Electric Corp|Semiconductor device and fabrication thereof|
    KR100319895B1|1999-12-03|2002-01-10|윤종용|Full CMOS SRAM cell|
    JP2001203347A|2000-01-18|2001-07-27|Mitsubishi Electric Corp|Semiconductor device and manufacturing method|
    US6522189B1|2000-10-02|2003-02-18|Broadcom Corporation|High-speed bank select multiplexer latch|
    US6614124B1|2000-11-28|2003-09-02|International Business Machines Corporation|Simple 4T static ram cell for low power CMOS applications|
    JP2002198443A|2000-12-26|2002-07-12|Nec Corp|Semiconductor device and its fabricating method|
    FR2826495B1|2001-06-22|2005-03-11|St Microelectronics Sa|BUFFER CIRCUIT, MEMORY CELLS INCORPORATING AND MEMORYING SUCH A MEMORY CELL|
    US6621727B2|2002-01-04|2003-09-16|Kuo-Tso Chen|Three-transistor SRAM device|
    US6674671B1|2002-08-14|2004-01-06|Broadcom Corp.|Circuit for lines with multiple drivers|
    US6924560B2|2003-08-08|2005-08-02|Taiwan Semiconductor Manufacturing Co., Ltd.|Compact SRAM cell with FinFET|
    JP4598483B2|2004-11-10|2010-12-15|パナソニック株式会社|Semiconductor device and manufacturing method thereof|
    KR100760910B1|2005-12-29|2007-09-21|동부일렉트로닉스 주식회사|SRAM Device Having Common Contact|
    US8943425B2|2007-10-30|2015-01-27|Google Technology Holdings LLC|Method and apparatus for context-aware delivery of informational content on ambient displays|
    KR101250984B1|2008-07-11|2013-04-03|삼성전자주식회사|Semiconductor device including driving transistors|
    法律状态:
    2002-03-28| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2005-09-23| FPAY| Fee payment|Year of fee payment: 4 |
    2009-09-16| FPAY| Fee payment|Year of fee payment: 8 |
    2013-08-28| FPAY| Fee payment|Year of fee payment: 12 |
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960026312A|KR100230740B1|1996-06-29|1996-06-29|A sram and manufacturing method thereof|
    KR96-26312||1996-06-29||
    US08/882,312|US5907502A|1996-06-29|1997-06-25|SRAM cell and method of manufacturing the same|
    US09/232,869|US6204538B1|1996-06-29|1999-01-15|SRAM cell|
    US09/756,060|US6372565B2|1996-06-29|2001-01-08|Method of manufacturing SRAM cell|US09/756,060| US6372565B2|1996-06-29|2001-01-08|Method of manufacturing SRAM cell|
    [返回顶部]